Transceiver module

ABSTRACT

A transceiver module includes a transceiver (PHY IC) having a status register and a control register to which whether or not to generate a status signal is set according to the cause of an error, and a DCU having registers which emulate the status and control registers. The PHY IC generates an Unmask signal specifying an error which occurs irrespective of the cause of the error, and outputs it to the DCU. The DCU writes the contents of the status register into a DCU status register as well as the host of the error based on the Unmask signal.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to a transceiver module for opticalcommunications.

2. Description of Related Art

There have been provided transceiver modules for optical communicationswhich are compliant with the IEEE802.3ae standard, for example. Atransceiver compliant with the IEEE802.3ae standard includes, forexample, an NV (Non-Volatile) register, a DOM (Digital OpticalMonitoring) register, an LASI (Link Alarm Status Interrupt) register,etc. which are XENPAK (common specifications of optical connectors andoptical transceivers which operate according to the XAUI (10 GigabitAttachment Unit Interface) protocol adopted by 10Gbit Ethernet(registered trademark) defined by the IEEE802.3ae standard) (refer tononpatent reference 1, for example).

A related art transceiver IC (referred to as a PHY IC from here on)which constitutes such a transceiver module mentioned above has bothIEEE registers which are used when carrying out communicationsprocessing and XENPAK registers which are defined by the above-mentionedstandard, those registers being implemented via hardware. Aserror-associated registers which belong to those registers, there existinterrelated registers (i.e., LASI_Status registers) holding the samecontents in the IEEE registers and XENPAK registers, respectively.

[Nonpatent reference 1]

“A Cooperation Agreement for 10 Gigabit Ethernet (registered trademark)Transceiver Package Issue3.0”, [online], 18th Sep. 2002 and XENPAK,[retrieved on Sep. 17, 2004], Internet URL<http://www.xenpak.org/MSA/XENPAK_MSA_R3.0.pdf>

In the related art transceiver module, when a change is made to thestructure and function of either the IEEE registers or the XENPAKregisters, it is necessary to perform the design and development of thePHY IC again so that the structure and function of the registers meetnew specifications.

On the other hand, when the structure and function of the XENPAKregisters which are built in the PHY IC are software-emulated by adevice control unit (referred to as a DCU from here on) which is an ICfor controlling the PHY IC and other peripheral functions, the structureand function of the XENPAK registers can be changed by changing asoftware program of the DCU which software-emulates the structure andfunction of the XENPAK registers.

However, while information about a high-speed error which is detectedonly by the PHY IC and which is associated with communicationsprocessing is stored in one of the XENPAK registers of the PHY IC, towhich information about errors can be set, information about a low-speederror which is detected only by the DCU and which is associated withinternal processing is stored in one of the XENPAK registers of the PHYIC, to which information about errors can be set. A problem is thereforethat a mismatch occurs between the contents of the register for storingerror information in the PHY IC and those in the DCU.

SUMMARY OF THE INVENTION

The present invention is made in order to solve the above-mentionedproblem, and it is therefore an object of the present invention toprovide a transceiver module which, when a DCU emulates registers of aPHY IC, can cancel a mismatch between the contents of the registers inthe PHY IC and those in the DCU, which is caused by the occurrence of ahigh-speed error which is detected only by the PHY IC and occurrence ofa low-speed error which is detected only by the DCU.

In accordance with the present invention, there is provided atransceiver module including: a physical-layer integrated circuit havinga physical-layer register unit including an error flag register to whicha bit value indicating occurrence of an error is set, and an errornotification control register to which a bit value indicating whether ornot to generate a first error signal for notifying the occurrence of theerror to a higher-layer device is set according to a cause of the error;and a control integrated circuit having a control-side register unitwhich emulates the structure and function of the physical-layer registerunit, in which the physical-layer integrated circuit generates a seconderror signal for notifying the error irrespective of the cause of theerror, and outputs the second error signal to the control integratedcircuit, and the control integrated circuit specifies the error detectedby the physical-layer integrated circuit based on the second errorsignal and generates the first error signal about this specified errorand delivers the first error signal to the higher-layer device, whilewriting contents of the error flag register of the physical-layerregister unit into an error flag register of the control-side registerunit.

Since the transceiver module according to the present invention includesthe physical-layer integrated circuit having the physical-layer registerunit including the error flag register to which a bit value indicatingoccurrence of an error is set, and the error notification controlregister to which a bit value indicating whether or not to generate afirst error signal for notifying the occurrence of the error to ahigher-layer device is set according to a cause of the error, and thecontrol integrated circuit having the control-side register unit whichemulates the structure and function of the physical-layer register unit,and the physical-layer integrated circuit generates the second errorsignal for notifying the error irrespective of the cause of the error,and outputs the second error signal to the control integrated circuit,and the control integrated circuit specifies the error detected by thephysical-layer integrated circuit based on the second error signal andgenerates the first error signal about this specified error and deliversthe first error signal to the higher-layer device. Therefore, thepresent invention offers an advantage of being able to cancel a mismatchbetween the contents of the registers in the physical-layer integratedcircuit and those of the registers in the control integrated circuit,which is caused by both the occurrence of an error (i.e., a high-speederror associated with communications processing) which is detected onlyby the physical-layer integrated circuit, and the occurrence of an error(i.e., a low-speed error associated with internal processing, such asmonitoring of a laser for transmission) which is detected only by thecontrol integrated circuit when the control-side register unit in thecontrol integrated circuit emulates the physical-layer register unit inthe physical-layer integrated circuit.

Further objects and advantages of the present invention will be apparentfrom the following description of the preferred embodiments of theinvention as illustrated in the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 2 of the present invention, and alarmsignal control processing carried out by the transceiver module;

FIG. 2 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 2 of the present invention, and alarmsignal control processing carried out by the transceiver module; and

FIG. 3 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 3 of the present invention, and alarmsignal control processing carried out by the transceiver module.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiment 1

FIG. 1 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 1 of the present invention, and alarmsignal control processing carried out by the transceiver module, andshows, as an example, an optical-communications transceiver module for10G-bit Ethernet (registered trademark) compliant with the IEEE802.3aestandard. The transceiver module 1 for optical communications inaccordance with this embodiment is roughly divided into a DCU 2 and a10Gb-PHY IC (referred to as a PHY IC from here on) 3 for transceiver.

The DCU (i.e., a control integrated circuit) 2 and PHY IC (i.e., aphysical-layer integrated circuit) 3 are connected to each other via abus 10 for general-purpose serial interface, e.g., an I2C (InternationalInstitute for Communications) serial bus. In the DCU 2 and PHY IC 3,MDIO (Management Data Input/Output) interface circuits 6 and 7 compliantwith the IEEE802.3ae establish a communication connection with a host 4that is a higher-layer device, respectively.

The PHY IC 3 has an XENPAK register group (i.e., a physical-layerregister unit) 8 in which an NVR register (referred to as NVR in thefigure) 8 a, a DOM register 8 b, and a LASI register, etc., which arenot shown, are disposed, these registers being compliant with theIEEE802.3ae standard, in addition to the MDIO interface circuit 7.

Since the XENPAK register group 8 is software-emulated by the DCU 2, thePHY IC 3 has a mode in which it does not respond to access to the XENPAKregister group 8 by way of the MDIO interface 5 from the host 4.Thereby, when access to the XENPAK registers of the transceiver module 1from the host 4 is made, a reply output from the PHY IC 3 can beprevented from colliding with a reply output from the DCU 2. In theillustrated example, in order to show that the PHY IC 3 is placed in themode, the XENPAK register group 8 of the PHY IC is enclosed by a dashedline, and a cross is added to the box of the XENPAK register group.

The DCU 2 includes the MDIO interface circuit 6, an SRAM 9, a CPU 16, aRAM 17, a timer (TM) 18, a watchdog timer (WT) 19, a digital-to-analogconverter (DA) 20, and an analog-to-digital converter (AD) 21. An XENPAKregister group (i.e., a control-side register unit) 9 a having the samestructure and function as those of the XENPAK register group 8 of thePHY IC 3 is implemented, via software which the CPU 16 executes, on theSRAM 9. In other words, the software emulates the XENPAK register group8 of the PHY IC 3 as the XENPAK register group 9 a.

The CPU (Central Processing Unit) 16 performs total control of the DCU 2which is disposed as a microcomputer which embodies operations andperipheral functions. The RAM 17 is used for storing software programswhich the CPU 16 executes, a work area, etc. The CPU 16 sets times tothe timer 18 and watchdog timer 19, respectively, and controls the wholeof the device by performing predetermined operations in response tointerrupt requests outputted from the timer 18 and watchdog timer 19.

The transceiver module 1 in accordance with this embodiment is alsoprovided with a laser 14 a for transmission, and a light receivingelement 14 b, and can transmit and receive data to and from outside thetransceiver module via optical cables 15 a and 15 b using the laser andlight receiving element. The PHY IC 3 furnishes data to be transmittedto the laser 14 a for transmission by way of an amplifier 13 a, and thelight receiving element 14 b furnishes received data to the PHY IC 3 byway of an amplifier 13 b.

The DCU 2 monitors the temperature of the laser 14 a for transmission,temperature of the transceiver module 1, a bias applied to the laser 14a for transmission, a bias applied to the light receiving element 14 b,and a power supply voltage applied to the laser 14 a for transmission,for example. The DCU 2 controls the bias applied to the laser 14 a fortransmission so that the output of the laser 14 a for transmission iskept constant.

When detecting an error, the DCU 2 writes digital information (i.e., abit value specifying the error) indicating the detection of the errorinto an LASI (Link Alarm Status Interrupt) register which is a componentof the XENPAK register group 9 a on the SRAM 9 which emulates the XENPAKregister group 8. The host 4 reads the contents of this LASI register ofthe XENPAK register group 9 a, and, when determining that it isundesirable that the transceiver module I will continue to operate,stops the operation of the transceiver module 1.

To be more specific, when detecting the occurrence of an abnormality,the DCU 2 furnishes an LASI signal (i.e., a first error signal) 12 forwarning the host 4 of the occurrence of the error to the host 4. Inresponse to the LASI signal, the host 4 refers to the XENPAK registergroup 9 a of the DCU 2 by way of the MDIO interface 5 and then gets toknow that the error has been detected. The LASI signal is a digitalsignal for specifying the error which is expressed in a form suitablefor recognition by the host 4, for example, and which is detected by thetransceiver module 1.

In addition to the above-mentioned LASI register to which informationindicating whether an error has occurred is set, the PHY IC 3 has analarm control register (referred to as a PHY_LASI_Control register fromhere on) (i.e., an error notification control register) to whichinformation indicating whether or not to notify the occurrence of theerror to outside the transceiver module according to the cause of theerror is set, in each set of the IEEE registers (not shown) and XENPAKregisters. Conventionally, even if an error which is ignored by thePHY_LASI_Control register has occurred, the transceiver module does notdeliver the LASI signal to any external circuit, such as the host 4.

In contrast, when detecting an error in communication data, the PHY IC 3in accordance with this embodiment 1 generates an error signal (referredto as a PHY_LASI_Unmask signal from here on) (i.e., a second errorsignal) 11 for causing the DCU 2 to generate an error signal in responseto every error event, and delivers the error signal 11 to the DCU 2without determining whether or not to deliver the LASI signal to thehost 4 under the control of the PHY_LASI_Control register. ThePHY_LASI_Unmask signal 11 is a signal having a digital value fornotifying and specifying an error detected by the PHY IC 3 irrespectiveof the contents of the PHY_LASI_Control register, that is, irrespectiveof the cause of the error, the digital value being expressed in a formsuitable for recognition by the DCU 2.

Next, the operation of the transceiver module in accordance with thisembodiment of the present invention will be explained. When a certainerror event occurs while the transceiver module 1 carries out acommunications operation, the transceiver module writes an error flagindicating the occurrence of the error into either the LASI register(referred to as the PHY_LASI_Status register from here on) (i.e., theerror flag register unit) in the XENPAK register group 8 of the PHY IC3, or the LASI register (referred to as the DCU_LASI_Status registerfrom here on) in the XENPAK register group 9 a, which is implemented onthe SRAM 9 via software in the DCU 2, according to the nature of theerror.

For example, when a high-speed error which is detected only by the PHYIC 3 and which is associated with communications processing occurs,information about the error is recorded into the PHY_LASI_Statusregister included in the PHY IC 3, and, when a low-speed error which isdetected only by the DCU 2 and which is associated with such processingas monitoring of the laser 14 a for transmission occurs, informationabout the error is recorded into the DCU_LASI_Status register includedin the DCU 2. Therefore, when these error recording operations arecarried out, there is a contradiction between the contents of thePHY_LASI_Status register, and those of the. DCU_LASI_Status register.

To solve this problem, when an error event associated with a high-speederror, the PHY IC 3 in accordance with this embodiment detects the errorand sets an error bit corresponding to the error event to thePHY_LASI_Status register of the XENPAK register group 8, andsimultaneously outputs a signal for notifying the occurrence of theerror to outside the transceiver module.

To be more specific, the PHY IC 3 sends the PHY_LASI_Unmask signal 11for causing the DCU 2 to generate an error signal in response to everyerror event to the DCU 2 without being controlled according to the valueset to the PHY_LASI_Control register which functions as an error signalgenerating control register which prohibits the generation of any errorsignal in response to a specific error event. The PHY IC 3 also sends anormal error signal (referred to as a PHY_LASI_Normal signal from hereon) (i.e., a third error signal) for prohibiting the DCU 2 fromgenerating any error signal in response to a specific error event to theDCU 2 by way of the PHY_LASI_Control register. The PHY_LASI_Normalsignal is a digital signal which specifies an error for which thegeneration of the LASI signal is controlled by the PHY_LASI_Controlregister.

At this time, the PHY_LASI_Unmask signal 11 from the PHY IC 3 isdelivered to a not-shown external interruption terminal of the DCU 2 sothat the DCU 2 can also detect the occurrence of an error event forwhich the DCU is prohibited from generating any error signal by the PHYIC 3. As a result, the DCU 2 outputs a secondary LASI signal 12indicating the occurrence of the error to the host 4 so as to notify theerror event to the host 4. The DCU 2 simultaneously copies the contentsof the PHY_LASI_Status register of the PHY IC 3 to the DCU_LASI_Statusregister therein, which emulates the PHY_LASI_Status register, by way ofan I2C interface 10.

It is assumed that the PHY IC 3 has a function of being able to accessinterrelated registers which are included in either the XENPAK registergroup 8 or at least the above-mentioned IEEE registers and XENPAKregisters by way of the I2C interface 10.

The PHY IC 3 outputs both the PHY_LASI_Unmask signal 11 andPHY_LASI_Normal signal to the DCU 2, as previously mentioned. As analternative, the PHY IC 3 outputs only the PHY_LASI_Unmask signal 11 tothe DCU 2.

As mentioned above, in accordance with this embodiment 1, thetransceiver module has both the PHY IC 3 having the XENPAK registergroup 8 including the PHY_LASI_Status register to which a bit valueindicating the occurrence of an error, and the PHY_LASI_Control registerto which a bit value indicating whether or not to generate an LASIsignal 12 for notifying the host 4 of the occurrence of the erroraccording to the nature of the error is set, and the DCU 2 having theXENPAK register group 9 a which emulates the structure and function ofthe XENPAK register group 8. When detecting an error, the PHY IC 3generates a PHY_LASI_Unmask signal 11 for causing the DCU 2 to generatethe LASI signal 12 for any cause of errors irrespective of the value setto the PHY_LASI_Control register, i.e., for notifying the occurrence ofthe error to the DCU 2 irrespective of the cause of the error, and thenoutputs the PHY_LASI_Unmask signal 11 to the DCU 2, and the DCU 2specifies the error detected by the PHY IC 3 based on thePHY_LASI_Unmask signal 11, generates the LASI signal 12 for the error,and then delivers the LASI signal 12 to the host 4. As a result, evenwhen a high-speed error which is detected only by the PHYIC3 occurs, theDCU 2 can know the occurrence of the error with the PHY_LASI_Unmasksignal 11 without always monitoring the contents of the PHY_LASI_Controlregister included in the PHY IC 3. The transceiver module can thus makethe contents of the DCU_LASI_Status register of the DCU 2 and those ofthe PHY_LASI_Status register of the PHY IC 3 match with each other,thereby preventing a contradiction from arising between the contents ofthese registers.

The DCU 2 checks to see whether an error event associated with each ofthe laser 14 a for transmission and light receiving element 14 b whichare monitored thereby occurs. Therefore, the DCU 2 can transmit an errorsignal (i.e., the LASI signal 12) which it has generatedcomprehensively, as well as other error signals (the PHY_LASI_Normalsignal and PHY_LASI_Unmask signal 11) associated with communicationsprocessing from the PHY IC 3, to the host 4 at a higher layer.Embodiment 2.

FIG. 2 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 2 of the present invention, and alarmsignal control processing carried out by the transceiver module, andshows, as an example, an optical-communications transceiver module for10G-bit Ethernet (registered trademark) compliant with the IEEE802.3aestandard. The same components as those of FIG. 1, or like components aredesignated by the same reference numerals as shown in FIG. 1, and theduplicated explanation of these components will be omitted hereafter.

Although the transceiver module 1 in accordance with this embodiment hasthe same basic structure as that according to above-mentioned embodiment1, the transceiver module 1 in accordance with this embodiment differsfrom that according to above-mentioned embodiment 1 in that a wired ORconnection is established between a normal error signal (referred to asa DCU_LASI_Normal signal from here on) (i.e., a fourth error signal) forprohibiting the generation of any error signal (i.e., a first errorsignal) with a DCU_LASI_Control register (not shown), and a normal errorsignal (referred to as a PHY_LASI_Normal signal from here on) (i.e., athird error signal) for prohibiting the generation of any error signalwith a PHY_LASI_Control register (not shown), and the result of alogical OR operation implemented on the DCU_LASI_Normal signal andPHY_LASI_Normal signal is an error signal (i.e., a first error signal)to be delivered to a host 4. The DCU_LASI_Normal signal is a digitalsignal for specifying an error for which the generation of the LASIsignal is controlled by the DCU_LASI_Control register which a DCU 2emulates.

Also in FIG. 2, since an XENPAK register group 8 is software-emulated bythe DCU 2, a PHY IC 3 has a mode in which it does not respond to accessto the XENPAK register group 8 by way of an MDIO interface 5 from thehost 4. In the illustrated example, in order to show that the PHY IC 3is placed in the mode, the XENPAK register group 8 is enclosed by adashed line, and a cross is added to the box of the XENPAK registergroup 8.

Next, the operation of the transceiver module in accordance with thisembodiment of the present invention will be explained. When an errorevent occurs while the transceiver module 1 carries out a communicationsoperation, the transceiver module writes an error flag indicating theoccurrence of the error into either a PHY_LASI_Status register in theXENPAK register group 8 of the PHY IC 3, or a DCU_LASI_Status registerin an XENPAK register group 9 a, which is implemented on an SRAM 9 viasoftware in the DCU 2, according to the nature of the error.

For example, when a high-speed error which is detected only by the PHYIC 3 and which is associated with communications processing occurs,information about the error is recorded into the PHY_LASI_Statusregister included in the PHY IC 3, whereas when a low-speed error whichis detected only by the DCU 2 and which is associated with suchprocessing as monitoring of a laser 14 a for transmission occurs,information about the error is recorded into the DCU_LASI_Statusregister included in the DCU 2. Therefore, when these error recordingoperations are carried out, there is a contradiction between thecontents of the PHY_LASI_Status register, and those of theDCU_LASI_Status register.

To solve this problem, when an error event associated with a high-speederror occurs, the PHY IC 3 in accordance with this embodiment detectsthe error and sets an error bit corresponding to the error event to thePHY_LASI_Status register of the XENPAK register group 8, and thenoutputs a signal for notifying the occurrence of the error to outsidethe transceiver module, like that of above-mentioned embodiment 1.

Like that of above-mentioned embodiment 1, the PHY IC 3 sends outs aPHY_LASI_Unmask signal (i.e., a second error signal) 11 for causing theDCU 2 to generate an error signal in response to every error event tothe DCU 2 without being controlled by the PHY_LASI_Control register ofthe XENPAK register group 8. The PHY IC 3 also sends out aPHY_LASI_Normal signal (i.e., a third error signal) for prohibiting theDCU 2 to generate an error signal in response to a specific error eventto the DCU 2 by way of the PHY_LASI_Control register.

At this time, the PHY_LASI_Unmask signal 11 from the PHY IC 3 isdelivered to a not-shown external interruption terminal of the DCU 2 sothat the DCU 2 can also detect the occurrence of an error event forwhich the DCU is prohibited from generating any error signal by the PHYIC 3. The DCU 2 simultaneously copies the contents of thePHY_LASI_Status register of the PHY IC 3 to the DCU_LASI_Status registertherein, which emulates the PHY_LASI_Status register, by way of an I2Cinterface 10.

The DCU_LASI_Normal signal which is sent out via the DCU_LASI_Controlregister and which is a normal error signal for prohibiting thegeneration of an error signal in response to a specific error event, andthe PHY_LASI_Normal signal which is sent out via the PHY_LASI_Controlregister and which is a normal error signal for prohibiting generationof an error signal in response to a specific error event are delivered,via a bus which wired-OR connects lines via which the DCU_LASI_Normalsignal and PHY_LASI_Normal signal are passed through, to the host 4.

Therefore, a signal having the result of a logical OR operationimplemented on digital values respectively indicated by thePHY_LASI_Normal signal and DCU_LASI_Normal signal is delivered, as anLASI signal indicating the occurrence of the error, to the host 4. As aresult, even if an error occurs in either the DCU 2 or PHY IC 3, thehost 4 can know the occurrence of the error from the result of a logicalOR operation implemented on the PHY_LASI_Normal signal andDCU_LASI_Normal signal.

As mentioned above, in accordance with this embodiment 2, the PHY IC 3outputs the PHY_LASI_Normal signal specifying an error for which thegeneration of the LASI signal is controlled according to the value setto the PHY_LASI_Control register, and the DCU2 outputs theDCU_LASI_Normal signal specifying an error for which the generation ofthe LASI signal is controlled according to the value set to theDCU_LASI_Control register of the XENPAK register group 9 a whichemulates the XENPAK register group 8, as well as an error which the DCU2 specifies based on the PHY_LASI_Unmask signal 11 and which is detectedby the PHY IC 3, and the transceiver delivers the result of a logical ORoperation implemented on digital values respectively indicated by thePHY_LASI_Normal signal and DCU_LASI_Normal signal respectively outputtedfrom the PHY IC 3 and DCU 2, as the LASI signal, to the host 4.Therefore, the transceiver can transmit both an error event associatedwith a low-speed operation which is detected by the DCU 2, and an errorevent associated with a high-speed operation which is detected by thePHY IC 3 to the host 4 at a high speed, thereby increasing the speed ofresponse of the whole of the system. Embodiment 3.

FIG. 3 is a diagram for explaining the structure of a transceiver modulein accordance with embodiment 3 of the present invention, and alarmsignal control processing carried out by the transceiver module, andshows, as an example, an optical-communications transceiver module for10G-bit Ethernet (registered trademark) compliant with the IEEE802.3aestandard. Although the transceiver module 1 in accordance with thisembodiment has the same basic structure as that according toabove-mentioned embodiment 1, the transceiver module 1 in accordancewith this embodiment differs from that according to above-mentionedembodiment 1 in that a PHY IC 3 transmits an LASI signal to a host 4.The same components as those of FIG. 1, or like components aredesignated by the same reference numerals as shown in FIG. 1, and theduplicated explanation of these components will be omitted hereafter.

In addition, also in FIG. 3, since an XENPAK register group 8 issoftware-emulated by a DCU 2, the PHY IC 3 has a mode in which it doesnot respond to access to the XENPAK register group 8 via an MDIOinterface 5 from the host 4. In the illustrated example, in order toshow that the PHY IC 3 is placed in the mode, the XENPAK register group8 is enclosed by a dashed line, and a cross is added to the box of theXENPAK register group 8.

Next, the operation of the transceiver module in accordance with thisembodiment of the present invention will be explained. When an errorevent occurs while the transceiver module 1 carries out a communicationsoperation, the transceiver module writes an error flag indicating theoccurrence of the error into either a PHY_LASI_Status register in theXENPAK register group 8 of the PHY IC 3, or a DCU_LASI_Status registerin an XENPAK register group 9 a, which is implemented on an SRAM 9 viasoftware in the DCU 2, according to the nature of the error.

For example, when a high-speed error which is detected only by the PHYIC 3 and which is associated with communications processing occurs,information about the error is recorded into the PHY_LASI_Statusregister included in the PHY IC 3, whereas when a low-speed error whichis detected only by the DCU 2 and which is associated with suchprocessing as monitoring of a laser 14 a for transmission occurs,information about the error is recorded into the DCU_LASI_Statusregister included in the DCU 2. Therefore, when these error recordingoperations are carried out, there causes a contradiction between thecontents of the PHY_LASI_Status register, and those of theDCU_LASI_Status register.

To solve this problem, when an error event associated with a low-speederror which the DCU 2 in accordance with this embodiment monitorsoccurs, the DCU 2 writes an error bit corresponding to the error eventto the PHY_LASI_Status register of the XENPAK register group 8 in thePHYIC3 via an I2C interface 10.

On the other hand, when an error event associated with a high-speederror, the PHY IC 3 in accordance with this embodiment detects the errorand sets an error bit corresponding to the error event to thePHY_LASI_Status register of the XENPAK register group 8, andsimultaneously outputs a signal for notifying the occurrence of theerror to outside the transceiver module.

To be more specific, the PHYIC3 delivers a PHY_LASI. Normal signalhaving a value according to the contents of the PHY_LASI_Status registerof the XENPAK register group 8 into which an error bit is written by theDCU 2 and those of the PHY_LASI_Control register, as an LASI signal(i.e., a first error signal) 12, to the host 4.

As mentioned above, in accordance with this embodiment 3, thetransceiver module has the PHY IC 3 having the XENPAK register group 8including the PHY_LASI_Status register to which a bit value indicatingthe occurrence of an error is set, and the DCU2 having the XENPAKregister group 9 a which emulates the XENPAK register group 8, and theDCU 2 writes a bit value specifying the occurrence of the error, whichis set to the DCU_LASI_Status register of the XENPAK register group 9 awhich emulates the XENPAK register group 8, into the PHY_LASI_Statusregister of the PHY IC 3 and the PHY IC 3 generates an LASI signal 12for notifying the occurrence of the error specified by the value set tothe PHY_LASI_Status register to the host 4 and then delivers the LASIsignal 12 to the host 4. As a result, when a high-speed error which isdetected only by the PHYIC3 occurs, the DCU 2 can know the occurrence ofthe error without always monitoring the contents of the PHY_LASI Controlregister included in the PHY IC 3. The transceiver module can thus makethe contents of the DCU_LASI_Status register of the DCU 2 and those ofthe PHY_LASI_Status register of the PHY IC 3 match with each other,thereby preventing a contradiction from arising between the contents ofthese registers.

The PHY IC 3 can manage an error event associated with communicationsprocessing which it monitors, as well as the error which is detected bythe DCU 2, and can therefore transmit an error signal (i.e., an LASIsignal-12) which it has generated comprehensively to the host 4 at ahigher layer.

A variant having the following structure can be made in above-mentionedembodiment 3. For all error events which the DCU 2 monitors and whichare not controlled by the DCU_LASI_Control register (not shown) of theXENPAK register group 9 a corresponding to the PHY_LASI_Control registerof the XENPAK register group 8, the DCU 2 delivers either both aDCU_LASI_Unmask signal (i.e., an error signal which the DCU generates bybypassing the DCU_LASI_Control register) (i.e., a fifth error signal)for causing the PHY IC 3 to generate an error signal (i.e., a firsterror signal), and a normal error signal (referred to as aDCU_LASI_Normal signal from here on) (i.e., a sixth error signal) forprohibiting the PHY IC 3 from generating an error signal for a specificerror event, or only the DCU_LASI_Unmask signal, by way of theDCU_LASI_Control register, to the PHY IC 3. The PHY IC 3 simultaneouslycopies the contents of the DCU_LASI_Status register of the DCU 2 to thePHY_LASI_Status register by way of the I2C interface 10.

The DCU_LASI_Unmask signal is a signal having a digital value fornotifying and specifying the error detected by the DCU 2 irrespective ofthe contents of the DCU_LASI_Control register, that is, irrespective ofthe cause of the error, the digital value being expressed in a formsuitable for recognition by the PHY IC 3. The DCU_LASI_Normal signal isa digital signal for specifying an error for which the generation of theLASI signal is controlled by the DCU_LASI_Control register.

As a result, the PHY IC 3 can also detect the occurrence of an errorevent which is detected only by the DCU 2 and for which the generationof any error signal is prohibited by the PHY IC 3 from theDCU_LASI_Unmask signal delivered thereto from the DCU 2. The PHY IC 3can therefore output a secondary LASI signal 12 about the error to thehost 4, and can notify the occurrence of the error event to the host 4.

Many widely different embodiments of the present invention may beconstructed without departing from the spirit and scope of the presentinvention. It should be understood that the present invention is notlimited to the specific embodiments described in the specification,except as defined in the appended claims.

1. A transceiver module comprising: a physical-layer integrated circuithaving a physical-layer register unit including an error flag registerto which a bit value indicating occurrence of an error is set, and anerror notification control register to which a bit value indicatingwhether or not to generate a first error signal for giving notificationof occurrence of the error to a higher-layer device is set according tocause of the error; and a control integrated circuit having acontrol-side register unit which emulates structure and function of saidphysical-layer register unit, wherein said physical-layer integratedcircuit generates a second error signal for giving notification of theerror irrespective of the cause of the error, and outputs the seconderror signal to said control integrated circuit, and said controlintegrated circuit specifies the error detected by said physical-layerintegrated circuit, based on the second error signal, and generates thefirst error signal about the error specified by said control integratedcircuit and delivers the first error signal to the higher-layer device,while writing contents of said error flag register of saidphysical-layer register unit into an error flag register of saidcontrol-side register unit.
 2. The transceiver module according to claim1, wherein said physical-layer integrated circuit outputs a third errorsignal for specifying an error for which the generation of the firsterror signal is controlled by said error notification control register,as well as the second error signal, to said control integrated circuit,and said control integrated circuit specifies the error detected by saidphysical-layer integrated circuit based on the second and third errorsignals, generates the first error signal about the error specified bysaid control integrated circuit, and delivers the first error signal tothe higher-layer device.
 3. The transceiver module according to claim 1,wherein said physical-layer integrated circuit outputs a third errorsignal for specifying an error for which the generation of the firsterror signal is controlled by said error notification control register,said control integrated circuit outputs a fourth error signal forspecifying the error for which the generation of the first error signalis controlled by said error notification control registers which isemulated by said control-side register unit, as well as the errordetected by said physical-layer integrated circuit which said controlintegrated circuit has specified based on the second error signal, andsaid transceiver module delivers a result of a logical OR operationimplemented on a digital value indicated by the third error signaloutput from said physical-layer integrated circuit, and a digital valueindicated by the fourth error signal output from said control integratedcircuit to the higher-layer device, as the first error signal.
 4. Atransceiver module comprising: a physical-layer integrated circuithaving a physical-layer register unit including an error flag registerto which a bit value indicating occurrence of an error is set, and anerror notification control register to which a bit value indicatingwhether to generate a first error signal giving notification of theoccurrence of the error to a higher-layer device is set according tocause of the error; and a control integrated circuit having acontrol-side register unit which emulates structure and function of saidphysical-layer register unit, wherein said control integrated circuitgenerates a second error signal for giving notification of the errorirrespective of the cause of the error, and outputs the second errorsignal to said physical-layer integrated circuit, and saidphysical-layer integrated circuit specifies the error detected by saidcontrol integrated circuits based on the second error signal, andgenerates the first error signal about the error specified by saidcontrol integrated circuit and delivers the first error signal to thehigher-layer device, while writing contents of said error flag registerof said control-side register unit into said error flag register of saidphysical-layer register unit.
 5. The transceiver module according toclaim 4, wherein said control integrated circuit outputs a third errorsignal for specifying an error for which the generation of the firsterror signal is controlled by said error notification control registerswhich said control integrated circuit emulates as part of thecontrol-side register unit, as well as the second error signal, to saidcontrol integrated circuit, and said control integrated circuitspecifies the error detected by said physical-layer integrated circuitbased on the second and third error signals, generates said first errorsignal about the error specified by said control integrated circuit, anddelivers the first error signal to the higher-layer device.
 6. Atransceiver module comprising: a physical-layer integrated circuithaving a physical-layer register unit including an error flag registerto which a bit value indicating occurrence of an error is set; and acontrol integrated circuit having a control-side register unit whichemulates structure and function of said physical-layer register unit,wherein said control integrated circuit writes a bit value specifying anerror and being set to an error flag register of said control-sideregister unit, which emulates said physical-layer register unit, intosaid error flag register of said physical-layer integrated circuit, andsaid physical-layer integrated circuit generates a first error signalindicating the occurrence of the error specified by the bit value set tosaid error flag register of said physical-layer register unit anddelivers the first error signal to a higher-layer device.